The present invention generally relates to a method for calculating high-resolution wafer parameter profiles.
Integrated circuit yields on wafers frequently follow patterns across the wafer. Analysis of these patterns is useful in determining the source of process variations or yield loss. An observed pattern can be matched against the physical characteristics of a process tool or the patterns observed by other techniques such as particle inspections.
Typically, the wafer patterns are observed by plotting yields or some other parametric value of a specific device by die in what is known as a wafer map. This is useful when working with obvious patterns that stand out given the die size or number of data points available to be plotted. This approach has limited value when dealing with very large die or when there is limited data from a given product or when the impact is relatively low compared to the background variation, i.e., a poor signal to noise ratio.
The typical approaches for generating wafer profiles are:                1) Stacking data from the die of many wafers of the same product into what is known as a stacked wafer map;        2) Using data from the smallest die sized product in order to have a higher spatial resolution; and        3) Using the data from methods 1 or 2 above to interpolate values in between die locations through the use of statistical smoothing algorithms. These results are sometimes known as response surface plots or contour maps.        
The foregoing approaches, however, are typically met with the following problems:                1) When using data from only one product there may be only a limited number of data points per die location availed from that product in the time frame of interest;        2) If the die size is relatively large for the selected product, the spatial resolution will be poor and important patterns will not be resolved; and        3) The accuracy of statistical interpolations using the above data will be limited in accuracy based on the data used.        